1. Field of the Invention
The present invention is related to a method of reading data at a high speed by detecting variations in voltage of a sense line during readout of data from a memory in which write data are, as in the case of a ROM and a microcode, previously determined.
2. Description of the Prior Art
A typical arrangement of a conventional memory data readout control circuit is depicted in FIG. 1.
A ROM circuit 1 is composed of a sense line electrifying charging unit 2, a sense line control unit 6, a sense line 13 and a sense amplifier 14. The numeral 10 represents a capacitance of the sense line. Before the memory data are read out, a control signal 5 becomes active, while sense line 13 is charged to a power supply voltage from power supply terminal 3 of sense line charging unit 2 via MOS transistor 4 or at a potential which drops due to fundamental device characteristics (e.g., a substrate effect) of a MOS transistor.
Subsequently, when a control signal 9 transmitted from an address decoder 11 becomes active, sense line 13 is discharged to an earth voltage via action of an NMOS transistor 8 of readout control unit 6. Whereas if control signal 9 does not become active, sense line 13 is kept at an elevated voltage, because NMOS transistor 8 remains OFF.
When data is read from ROM circuit 1, a control signal 15 becomes active, and any voltage on sense line 13 is detected by sense amplifier 14. Then, a readout result is output from output terminal 18. For instance, where sense line 13 has been discharged to ground or zero voltage, a logic value of 0 is read out. When sense line 13 is charged at the elevated voltage, a logic value 1 is read out.
This type of device is exemplified in Japanese Patent Laid-Open Publication No. 59-24493.
Although suitable for the purposes intended, the following disadvantages are inherent in the conventional construction when reading out the data from the memory. For example, as the size of the memory increases, the length of each line increases. The increase in length of the sense line causes a corresponding increase in capacitance of the sense line. Capacitance in the sense line increases the time it takes to read out data from the memory, because the MOS transistor controlling the sense line is relatively small in configuration but has a large turn on resistance. Also, an increase in speed of a memory read operation can be achieved by using a sense amplifier circuit (e.g., a sense amplifier using a differential amplifier circuit) but the structure becomes complicated. Moreover, a sense amplifier circuit has to be used for every bit so large chip area is required.